PXIE-8840QC

Brand: NI

Type:PXIE-8840QC

Origin: the United States

Warranty: 365 days

Colour: new/used

Shipping method: Courier delivery

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5. The EPROM and Flash are sized by the MCchip ASIC from an 8-bit private bus to the 32-bit MPU local bus. Because the device size is less than the allocated memory map for some entries, the device contents repeat for those entries. If jumper GPIO3 is installed, the Flash device is accessed. If GPIO3 is not installed, the EPROM is accessed. 6. The Flash and EPROM are sized by the MCchip ASIC from an 8-bit private bus to the 32-bit MPU local bus. Because the device size is less than the allocated memory map for some entries, the device contents repeat for those entries. If jumper GPIO3 is installed, the PROM device is accessed. If GPIO3 is not installed, the Flash is accessed. 7. These areas are not decoded unless one of the programmable decoders are initialized to decode this space. If they are not decoded, an access to this address range will generate a local bus timeout. The local bus timer must be enabled. Table 3-2 focuses on the ‘‘Local I/O Devices’’ portion of the local bus main memory map

1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory map, refer to the following detailed peripheral device memory maps. 2. The SCC is an 8-bit device located on an MCchip private data bus. Byte access is required. $FFF58280 - $FFF582FF IPIC IP_c ID D16 128 B 1 $FFF58300 - $FFF5837F IPIC IP_d I/O D16 128 B 1 $FFF58380 - $FFF583FF IPIC IP_d ID Read D16 128 B 1 $FFF58400 - $FFF584FF IPIC IP_ab I/O D32-D16 256 B 1 $FFF58500 - $FFF585FF IPIC IP_cd I/O D32-D16 256 B 8 $FFF58600 - $FFF586FF IPIC IP_ab I/O Repeated D32-D16 256 B 1 $FFF58700 - $FFF587FF IPIC IP_cd I/O Repeated D32-D16 256 B 8 $FFF58800 - $FFF5887F Reserved - - 128 B 1 $FFF58880 - $FFF588FF Reserved - - 128 B 1 $FFF58900 - $FFF5897F Reserved - - 128 B 1 $FFF58980 - $FFF589FF Reserved - - 128 B 1 $FFF58A00 - $FFF58A7F Reserved - - 128 B 1 $FFF58A80 - $FFF58AFF Reserved - - 128 B 1 $FFF58B00 - $FFF58B7F Reserved - - 128 B 1 $FFF58B80 - $FFF58BFF Reserved - - 128 B 1 $FFF58C00 - $FFF58CFF Reserved - - 256 B 1 $FFF58D00 - $FFF58DFF Reserved - - 256 B 1 $FFF58E00 - $FFF58EFF Reserved - - 256 B 1 $FFF58F00 - $FFF58FFF Reserved - - 256 B 1 $FFFBC000 - $FFFBC01F IPIC Registers D32-D8 2 KB 1 $FFFBC800 - $FFFBC81F Reserved - - 2 KB 1 $FFFBD000 - $FFFBFFFF Reserved - - 12 KB 4 $FFFC0000 - $FFFC7FFF MK48T08 (BBRAM, TOD Clock) D32-D8 32 KB 1 $FFFC8000 - $FFFCBFFF MK48T08 & Disable Flash writes D32-D8 16 KB 1, 7 $FFFCC000 - $FFFCFFFF MK48T08 & Enable Flash writes D32-D8 16 KB 1, 7 $FFFD0000 - $FFFEFFFF Reserved - - 128 KB 4 Table 3-2. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed Port Width Size Notes Memory Maps MVME162/D2 3-7 3 3. Writes to the LCSR in the VMEchip2 must be 32 bits. LCSR writes of 8 or 16 bits terminate with a TEA signal. Writes to the GCSR may be 8, 16 or 32 bits. Reads to the LCSR and GCSR may be 8, 16 or 32 bits. Byte reads should be used to read the interrupt vector. 4. This area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 5. Size is approximate. 6. Port commands to the 82596CA must be written as two 16-bit writes: upper word first and lower word second. 7. Refer to the Flash and EPROM Interface section in the MCchip description in Chapter 3. Detailed I/O Memory Maps Tables 3-3 through 3-12 provide detailed memory maps for the VMEchip2, the MCchip, the Zilog Z85230 serial communications controller, the Intel 82596CA LAN controller, the NCR 53C710 SCSI controller, the IPIC chip, and the MK48T08 BBRAM/TOD Clock.

2.